Magnetic memory architecture with shared current line

ABSTRACT

The present invention relates to magnetic or magnetoresistive random access memories (MRAMs). The present invention provides an array with magnetoresistive memory cells arranged in logically organized rows and columns, each memory cell including a magnetoresistive element ( 32 A,  32 B). The matrix comprises a set of column lines ( 34 ), a column line ( 34 ) being cells of a column. A column line ( 34 ) is shared by two adjacent columns, the shared column line ( 34 ) having an area which extends a continuous conductive strip which is magnetically couplable to the magnetoresistive element ( 32 A,  32 B) of each of the memory cells of a column. A column line ( 34 ) is shared by two adjacent columns, the shared column line ( 34 ) having an area which extends over substantially the magnetoresistive elements of the two adjacent columns sharing that column line. According to the present invention, the array furthermore comprises at least one supplementary column line ( 36 A,  36 B) per column for generating a localized magnetic field in the magnetoresistive elements ( 32 A,  32 B) of one of the adjacent columns sharing the column line ( 34 ). It is an advantage of the present invention that a higher density of the memory cells can be obtained, thus reducing space required to make a MRAM memory.

The present invention relates to magnetic or magnetoresistive randomaccess memories (MRAMs), and more particularly to a method and a devicefor creating higher magnetic fields at maximum current density.

Magnetic or Magnetoresistive Random Access Memory (MRAM) is currentlybeing considered by many companies as a successor to flash memory. Ithas the potential to replace all but the fastest static RAM (SRAM)memories. It is a non-volatile memory device, which means that no poweris required to sustain the stored information. This is seen as anadvantage over most other types of memory.

The MRAM concept was originally developed at Honeywell Corp. USA, anduses magnetization direction in a magnetic multilayer device asinformation storage and the resultant resistance difference forinformation readout. As with all memory devices, each cell in an MRAMarray must be able to store at least two states which represent either a“1” or a “0”.

Different kinds of magnetoresistive (MR) effects exist, of which theGiant Magneto-Resistance (GMR) and Tunnel Magneto-Resistance (TMR) arecurrently the most important ones. The GMR effect and the TMR orMagnetic Tunnel Junction (MTJ) or Spin Dependent Tunneling (SDT) effectprovide possibilities to realize a.o. non-volatile magnetic memories.These devices comprise a stack of thin films of which at least two areferromagnetic or ferrimagnetic, and which are separated by anon-magnetic interlayer. GMR is the magneto-resistance for structureswith conductor interlayers and TMR is the magneto-resistance forstructures with dielectric interlayers. If a very thin conductor isplaced between two ferromagnetic or ferrimagnetic films, then theeffective in-plane resistance of the composite multilayer structure issmallest when the magnetization directions of the films are parallel andlargest when the magnetization directions of the films areanti-parallel. If a thin dielectric interlayer is placed between twoferromagnetic or ferrimagnetic films, tunneling current between thefilms is observed to be the largest (or thus resistance to be thesmallest) when the magnetization directions of the films are paralleland tunneling current between the films is the smallest (or thusresistance the largest) when the magnetization directions of the filmsare anti-parallel.

Magneto-resistance is usually measured as the percentage increase inresistance of the above structures going from parallel to anti-parallelmagnetization states. TMR devices provide higher percentagemagneto-resistance than GMR structures, and thus have the potential forhigher signals and higher speed. Recent results indicate tunnelinggiving over 40% magneto-resistance, compared to 6-9% magneto-resistancein good GMR cells.

An MRAM comprises a plurality of magnetoresistive memory units 1arranged in an array. One such prior art memory unit 1 is shown inFIG. 1. Each memory unit 1 comprises a magnetoresistive memory element2, a first intersection of a digit line 4 and a bit line 6, and a secondintersection of the bit line 6 and a word line 8. The memory units 1 arecoupled in series in columns by means of the bit lines 6 and coupled inseries in rows by means of the digit lines 4 and word lines 8, thusforming the array. The magnetoresistive memory elements 2 used may forexample, but not limited thereto, be magnetic tunnel junctions (MTJs).

MTJ memory elements 2 generally include, as shown in FIG. 2, a layeredstructure comprising a fixed or pinned layer 10, a free layer 12-and adielectric barrier 14 in between. The MTJ memory element 2 furthermorecomprises a non-magnetic conductor forming a lower electrical contact22, and an upper contact 16 on the free magnetic layer 12. The pinnedmagnetic layer 10 and the free magnetic layer 12 may both be composed ofe.g. NiFe, and the dielectric barrier layer 14 may e.g. be made of AlOx.By applying a small voltage over the sandwich of ferromagnetic orferrimagnetic layers 10, 12 with the dielectric 14 therebetween,electrons can tunnel through the dielectric barrier 14.

The pinned layer 10 of magnetic material has a magnetic vector thatalways points in the same direction. The magnetic vector of the freelayer 12 is free, but constrained by the physical size of the layer, topoint in either of two directions: parallel or anti-parallel with themagnetization direction of the pinned layer 10.

An MTJ memory element 2 is used by connecting it in a circuit such thatelectricity can flow vertically through the element 2 from one of themagnetic layers to the other. The MTJ unit 1 can be electricallyrepresented by a resistor R in series with a switching element such as atransistor T, as shown in FIG. 1. The size of the resistance of theresistor R depends on the orientation of the magnetic vectors of thefree and pinned magnetic layers of the memory element 2. The MTJ element2 has a relatively high resistance (HiRes) when the magnetic vectorspoint in opposite directions, and it has a relatively low resistance(LoRes) when the magnetic vectors point in the same direction.

A diagrammatic elevational view of a 2×2 array of prior art memory unitsis shown in FIG. 2. In an MRAM array, comprising a plurality of MRAMunits, orthogonal conductive lines 4, 6 pass under and over each bit ormemory element 2, carrying current that produces a switching field. Eachbit is designed so that it will not switch when current is applied tojust one line, but will switch when current is flowing through bothlines 4, 6 that cross at the selected bit (switching will occur only ifthe magnetic vector of the free layer is not in accordance with thedirection of the switching field).

Digit lines 4 and bit lines 6 are provided in an array of MTJ memoryunits or cells 1, where the digit lines 4 travel along the rows of thearray on one side of the memory elements 2, and the bit lines 6 traveldown the columns of the array on the opposite side of the memoryelements 2. The structure in FIG. 2 is partially inverted for claritypurposes: digit lines 4 physically run underneath the MTJ elements 2 (atthat side of the MTJ elements 2 oriented towards the substrate in whichthe transistor T is provided), and bit lines 6 physically run over theMTJ elements 2 (at that side of the MTJ elements 2 oriented away fromthe substrate in which the transistor T is provided). However, if drawnthat way, the bit lines 6 would obscure the magnetoresistive elements 2,which are the more relevant parts of the drawing.

The memory element 2 is connected to the transistor T by means of aninterconnect layer 16 and a plurality of metalization layers 18 and vias20. There is a galvanic connection 22 between the memory element 2 andthe bit line 6. The transistor T of each memory unit 1 is connected to aground line 24.

In write or program mode, required currents flow through selected digitlines 4 and bit lines 6 so that at their intersection a peak magneticfield is generated, sufficient to switch the polarization of the freelayer 12 of the MTJ element 2, so as to switch the resistance of the MTJunit 2 from the LoRes (low resistance) state to the HiRes (highresistance) state or vice versa (depending on the direction of thecurrent through the bit line 6). At the same time, the switching elementsuch as transistor T in the selected memory unit 1 (the memory unit atthe intersection of the selected digit line 4 and the selected bit line6) is in the cut-off state, for example by keeping the voltage on theword line 8 low (0 volt in case the switching element is a transistorT). The currents in the selected digit line 4 and the selected bit line6 are such that together they provide a magnetic field able to changethe direction of the magnetic vector of the free layer of the selectedmemory element, but the current in either strip by itself is not able tochange the storage state. Therefore only the selected memory element iswritten, not any of the other memory elements on the same selected digitline 4 or bit line 6.

FIG. 3 diagrammatically illustrates a typical integration scheme forprior art high-density MRAM-cells 1. Magnetic fields are created on-chipby sending currents through bit lines 6 and digit lines 4, in generalcalled current lines, and are proportional to the current through thesecurrent lines. For obtaining higher magnetic fields, higher currentsneed to be used. However, low power applications will require lowcurrents. Those are contradictory requirements. Scaling of MRAMtechnology into the sub-100 nm area is desirable in order to get smallermemories, but it is not straightforward. Scaling laws are also appliedto the current lines, in particular to their cross-section. The currentdensity in a current line is limited to ˜10⁷ A/cm², a typicalelectromigration limit for Cu. At higher current densities,electromigration takes place, i.e. metal atoms migrate in the currentline, resulting in a break in the metal line. The above-mentioned limitsets an upper limit to the current in a Cu current line to 1 mA per 100nm×100 nm section. In other words, the magnetic field amplitude whichcan be generated when scaling down prior art magnetoresistive memorydevices is limited. Due to the smaller cross-section of the currentlines when scaling down, in combination with a fixed electromigrationlimit, the magnetic field generation does not scale properly. From FIG.3 can be seen that the digit lines have an undesirable geometry (widthsmaller than height).

Moreover, in order to preserve long-term thermal stability of the databits, switching fields typically increase when scaling down MRAMdevices. Magnetic elements typically have some aspect ratio to stabilizefavorable magnetization directions by shape anisotropy. However, smallerdimensions lead to increasing switching fields for a fixed aspect ratio.Therefore, the aspect ratio should be reduced for smaller devices. Onthe other hand, long-term thermal stability, i.e. data retention,requires a certain minimal energy barrier (K_(u)V) against switching,which is basically setting a minimum value for the switching field(˜K_(u)).

In US 2002/0057593, a thin film magnetic memory device having a highlyintegrated memory array is described. A top view and a cross-sectionalview respectively are shown in FIG. 9. Read word lines and write wordlines 80 are provided corresponding to the respective memory cell rows,and bit lines 81 and reference voltage lines are provided correspondingto the respective memory cell columns. Adjacent memory cells 82 share atleast one of these signal lines, for example the bit lines 81. As aresult, the pitches of the signal lines provided in the entire memoryarray can be widened. Thus, the memory cells can be efficientlyarranged, achieving improved integration of the memory array. However,in order to conduct the data read and write operations normally, aplurality of memory cells 82 simultaneously selected by a single bitline 81 must not simultaneously receive a data write magnetic field fromthe word write line 80. Accordingly, the cells 82 are arrangedalternately. FIG. 9 illustrates the alternate filling of the memorymatrix. This embodiment has the disadvantage that there is a significantloss of density. Some density improvement is possible by shifting thememory cells 82 closer together, e.g. by aligning the via contacts tothe transistor, as shown in FIG. 10. What is shown in dashed lines inthe cross-sectional view of FIG. 10, are elements on a neighboring writeword line 80. As the signal line (under bit line 81) is functional, onlya small improvement can be obtained in the width of the bit line 81.This embodiment still has the disadvantage that a lot of memory densityis lost.

It is an object of the present invention to provide a device and methodfor improving magnetic field generation. Improved magnetic fieldgeneration includes: generating a higher magnetic field for a givencurrent density and/or decreasing cross-talk to neighboring,non-selected memory cells, and/or creating a better uniformity of themagnetic field throughout the memory device.

The above objective is accomplished by a method and device according tothe present invention.

The present invention provides an array with magnetoresistive memorycells arranged in logically organized rows and columns, each memory cellincluding a magnetoresistive element. The matrix comprises a set ofcolumn lines, a column line being a continuous conductive strip which ismagnetically couplable to the magnetoresistive element of each of thememory cells of a column. A column line is shared by two adjacentcolumns, the shared column line having an area which extends oversubstantially the magnetoresistive elements of the two adjacent columnssharing that column line. According to the present invention, the arrayfurthermore comprises at least one supplementary column line per columnfor generating a localized magnetic field in the magnetoresistiveelements of one of the adjacent columns sharing the column line. It isan advantage of the present invention that density of the memory cellscan be improved with respect to prior art memory devices with sharedcolumn lines, thus reducing space required to make an MRAM memory.

According to an embodiment of the present invention, a supplementarycolumn line may form a return current path for current carried by acolumn line. A magnetic field created from current flowing through thereturn current path is used to increase the magnetic field in the memoryelements of a selected column. The increased field provides betterwriting to a memory element for example.

The array may furthermore comprise a set of row lines, each row linebeing a continuous conductive strip which is magnetically couplable tothe magnetoresistive element of each of the memory cells of a row. Acombined magnetic field generated by current through a row linecorresponding to a selected memory cell, by current through a columnline corresponding to the selected memory cell, and by current throughthe return column line corresponding to the selected memory cell issufficiently high for switching (dependent on the content of the memorycell) the magnetic status of the magnetoresistive element of theselected memory cell. A magnetic field generated by current through anyone of the named current lines, or a combination of magnetic fieldsgenerated by not all the named current lines, is preferably not highenough to provide a switching field. It is an advantage of the presentinvention that lower current levels can be sent through the row line,column line and return line, while still a switching field is generated.

In an embodiment of the present invention, a column line and asupplementary column line are provided at opposite sides of a column ofmagnetoresistive elements.

A column of magnetoresistive elements may be placed offset in arow-direction with regard to a center of a supplementary column line.

The column lines and/or the supplementary column lines and/or the rowlines may be provided with a flux guiding cladding layer. An advantageof such cladding layer is that the magnetic fields in the column linesare more concentrated, and that cross-talk is reduced, hence unwantedprogramming of neighboring bits is avoided.

The present invention also provides a non-volatile memory comprising thearray with magnetoresistive memory cells as described above, i.e. anarray as described above, provided with a.o. suitable row and columndrivers.

The present invention furthermore provides a method of operating anarray with magnetoresistive memory cells arranged in logically organizedrows and columns, each cell including a magnetoresistive element. Themethod comprises: applying current to a row line, applying current to acolumn line shared by two columns, and applying current to at least onesupplementary column line for generating a localized magnetic field inone of the memory elements on the column line.

The present invention also provides a method of manufacturing an arraywith magnetoresistive memory cells. The method comprises: providingmagnetoresistive memory cells arranged in logically organized rows andcolumns, each cell including a magnetoresistive element, providing a setof column lines, a column line being a continuous conductive strip whichis magnetically couplable to the magnetoresistive element of each of thememory cells of a column, a column line being shared by two adjacentcolumns, the shared column line having an area which extends oversubstantially the magnetoresistive elements of the two adjacent columnssharing that column line, and providing at least one supplementarycolumn line per column for generating a localized magnetic field in themagnetoresistive elements of one of the adjacent columns sharing thecolumn line.

These and other characteristics, features and advantages of the presentinvention will become apparent from the following detailed description,taken in conjunction with the accompanying drawings, which illustrate,by way of example, the principles of the invention. This description isgiven for the sake of example only, without limiting the scope of theinvention. The reference figures quoted below refer to the attacheddrawings.

FIG. 1 is an electrical-representation of an MRAM unit for connection inan array according to the prior art.

FIG. 2 is a diagrammatic elevational view of a 2×2 array of MTJ unitsaccording to the prior art.

FIG. 3 is a top view and a cross-sectional view of a typical integrationlayout for a 1T-1MTJ MRAM according to the prior art.

FIG. 4 is a top view and a cross-sectional view of an integration layoutwith shared column line according to an embodiment of the presentinvention, the cross-sectional view showing supplementary column linesaccording to the present invention, which have been removed for the topview.

FIG. 5 illustrates the shared current line concept of the presentinvention in a 1T-1MTJ MRAM.

FIG. 6 is a graph of the calculated magnetic field component profile fora selected and a non-selected column sharing a column line. A first caseis represented in which a return path is formed by a supplementarycolumn line influencing the magnetic field at the selected column. Asecond case is represented in which a return path is formed by a firstsupplementary column line influencing the magnetic field at the selectedcolumn, and a second supplementary column line influencing the magneticfield at the non-selected column.

FIG. 7 is a graph showing a calculated 3-dimensional magnetic fieldamplitude, taking into account currents in the row line, the columnline, the supplementary column line influencing the magnetic field atthe selected column and the supplementary column line influencing themagnetic field at the non-selected column.

FIG. 8 illustrates the concept of the present invention according to afurther embodiment with cladding of current lines.

FIG. 9 is a top view and a cross-sectional view of an integration layoutwith shared column line according to the prior art.

FIG. 10 is a top view and a cross-sectional view of an integrationlayout with shared column line according to the prior art, with densityimprovement.

FIG. 11 is a schematic explanation of the creation of different currentpaths.

FIG. 12 is a schematic diagram of an MRAM architecture according to thepresent invention for word-parallel write operations.

FIG. 13 is a schematic diagram of a further embodiment of the presentinvention with a single current source for simultaneously providing anequally distributed current to different bits in a word.

FIG. 14 schematically illustrates a serial single current sourceword-parallel MRAM.

In the different figures, the same reference figures refer to the sameor analogous elements.

The present invention will be described with respect to particularembodiments and with reference to certain drawings but the invention isnot limited thereto but only by the claims. The drawings described areonly schematic and are non-limiting. In the drawings, the size of someof the elements may be exaggerated and not drawn on scale forillustrative purposes. Where the term “comprising” is used in thepresent description and claims, it does not exclude other elements orsteps. Where an indefinite or definite article is used when referring toa singular noun e.g. “a” or “an”, “the”, this includes a plural of thatnoun unless something else is specifically stated.

Furthermore, the terms first, second, third and the like in thedescription and in the claims, are used for distinguishing betweensimilar elements and not necessarily for describing a sequential orchronological order. It is to be understood that the terms so used areinterchangeable under appropriate circumstances and that the embodimentsof the invention described herein are capable of operation in othersequences than described or illustrated herein.

According to an embodiment of the present invention, as illustrated inFIG. 4, a matrix 30 of magnetoresistive memory cells 31, each memorycell 31 comprising a magnetoresistive memory element 32, is logicallyorganized in rows and columns. Throughout this description, the terms“horizontal” and “vertical” are used to provide a coordinate system andfor ease of explanation only. They do not need to, but may, refer to anactual physical direction of the device. Furthermore, the terms “column”and “row” are used to describe sets of array elements which are linkedtogether. The liking can be in the form of a Cartesian array of rows andcolumns however the present invention is not limited thereto. As will beunderstood by those skilled in the art, columns and rows can be easilyinterchanged and it is intended in this disclosure that these terms beinterchangeable. Also, non-Cartesian arrays may be constructed and areincluded within the scope of the invention. Accordingly the terms “row”and “column” should be interpreted widely. To facilitate in this wideinterpretation, the claims refer to logically organized rows andcolumns. By this is meant that sets of memory elements are linkedtogether in a topologically linear intersecting manner however, that thephysical or topographical arrangement need not be so. For example, therows may be circles and the columns radii of these circles and thecircles and radii are described in this invention as “logicallyorganized” rows and columns. The terms “row” and “column” areinterchangeable. Also, specific names of the various lines, e.g. bitline and word line, or row line and column line, are intended to begeneric names used to facilitate the explanation and to refer to aparticular function and this specific choice of words is not intended toin any way limit the invention. It should be understood that all theseterms are used only to facilitate a better understanding of the specificstructure being described, and are in no way intended to limit theinvention.

According to the present invention, column lines 34 are provided, whichare continuous conductive strips, e.g. copper lines, which aremagnetically couplable to the magnetoresistive elements 32 of a columnin the array 30. These column lines 34 are each shared by two adjacentcolumns 35A, 35B of magnetoresistive elements 32 in the array 30. Thearea of a column line 34 is such that it substantially extends over atleast the magnetoresistive elements 32 of both adjacent columns 35A, 35Bsharing the column line 34, as illustrated in FIG. 4, and this for everyrow. The area of the column line 34 may be, but does not need be, so asto extend over substantially the complete width of both columns 35A,35B. By sharing a column line 34 over two adjacent columns 35A, 35Baccording to the present invention, a single current line is createdwith a much larger cross-section than each of the current lines 4 foradjacent columns in the prior art MRAM devices, as can be seen bycomparing FIG. 3 with FIG. 4. Contrary to the prior art, two memoryelements 32 in two different columns 35A, 35B sharing one and the samecolumn line 34 are provided on one single row.

The interleave-mirrored structure of memory elements 32 as representedin FIG. 3 and in FIG. 4 is used to save a transistor contact by sharingone contact between neighboring transistors (not represented in FIGS. 3and 4).

As illustrated in FIG. 4 and more schematically in FIG. 5, rectangularcurrent lines, column lines 34, with a height H smaller than a width Ware possible, even when scaling down magnetoresistive memory devices,even in a sub-100 nm design. The use of a column line 34 with height Hsmaller than width W gives rise to more homogeneous magnetic fieldsbeing created. Moreover, the cross-section of the shared column line 34according to the present invention is roughly tripled, which impliesthat a peak current through that column line 34 can significantlyincrease without danger for electromigration.

In order to generate a localized magnetic field in one of the bits-ormemory elements 32 on the shared column line 34, for example memoryelement 32B, not only a magnetic field has to be generated by sendingcurrent through an appropriate row line 37, but, according to thepresent invention, also a further magnetic field has to be generated bysending current through an appropriate supplementary column line 36B.Row lines 37 are continuous conductive strips, e.g. copper lines, whichare magnetically couplable to the magnetoresistive elements 32 of a rowin the array 30. Supplementary column lines 36, 36A, 36B are continuousconductive strips, e.g. copper lines, which are magnetically couplableto the magnetoresistive elements 32 of a column 35A, 35B in the array30. Preferably the supplementary column lines 36 and the shared columnlines 34 are located each at opposite sides of a column of memoryelements 32. The supplementary column lines 36 may be separately andindependently driven column lines, the magnetic field of whichinfluences at least the memory elements 32 of a selected column 35B ofthe columns 35A, 35B sharing the column line 34, so as to increase thegenerated magnetic field at the memory elements 32 of that selectedcolumn 35B. The supplementary column line 36 may furthermore influencethe memory elements 32 of a non-selected column 35A of the columns 35A,35B sharing the column line 34, so as to decrease the generated magneticfield at the memory elements 32 of that non-selected column 35A.Alternatively, the magnetic field generated by the supplementary columnline 36 may influence the memory elements 32B of a selected column 35Bmore than the memory elements 32 of the non-selected column 35A of theadjacent columns 35A, 35B sharing the column line 34. According to anembodiment, the supplementary column lines 36 may be return path linesfrom column lines 34. The supplementary column line 36 may be a singlecurrent line, or it may comprise a plurality of current lines. Part ofthe current in the supplementary column line 36, e.g. in case thesupplementary column line 36 consists of a plurality of current lines,may be used to create an opposite magnetic field at the location of thebits or memory elements 32 of the non-selected column 35A, in order toreduce or annihilate the magnetic field present there as generated bythe column line 34. The other part of the current in the supplementarycolumn line 36 is used to increase the magnetic field at the location ofthe bit memory elements of the selected column 35B. The supplementarycolumn lines 36A, 36B may be placed offset in a row-direction withregard to a corresponding column 35A, 35B of memory elements 32.Alternatively, the supplementary column lines 36A, 36B may be placedsymmetrically in a row-direction with regard to a corresponding column35A, 35B of memory elements 32.

A supplementary column line 36 may be created in a standard metal layerin semiconductor processing; and can thus easily be-incorporated inexisting magnetic memory production processing such as e.g. CMOSprocessing.

In the following, the concept of the present invention is demonstratedusing current line geometries typical for a CMOS090 process. Thegeometries used for the calculations are summarized in Table 1. Lines34, 37, 36A and 36B are column line 34, row line 37, and first andsecond supplementary current lines 36A, 36B respectively. As an example,a memory cell 32B in column 35B has to be written with either of twobinary values; e.g. “0” or “1”.

TABLE 1 Current Width Height Distance Offset Line (mA) (nm) (nm) (nm)(nm) 34 1 540 325 110 0 37 0.94 160 140 50 0 36A 1 500 250 400 −320 36B−2 500 250 400 320“Distance” is the distance between the free layer of a memory element32, 32A, 32B closest to the relevant line 34, 37, 36A, 36B, and asurface of the line 34, 37, 36A, 36B closest to the memory element 32,32A, 32B. “Offset” is the distance between the center of a column line34, and the center of the supplementary column lines 36A, 36Brespectively.

As an example, in the embodiment of table 1, the current level ofsupplementary column line 36B equals the sum of the current levels ofcolumn line 34 and supplementary column line 36A. Hence it is possibleto design a system in which supplementary column line 36B forms a returncurrent path for both column line 34 and supplementary column line 36A.A single current source can be provided, which can generate all currentsinvolved.

By directing the current into the shared column line 34 and one of thesupplementary column lines 36A, 36B, and returning it through the othersupplementary column line, or by sending it through one of thesupplementary column lines 36A, 36B and returning it through the sharedcolumn line 34 and the other supplementary column line, a unipolarcurrent source 40 can be used. Depending on the choice of thesupplementary column line 36A, 36B for the functional return path, aselection of one of the columns 35A, 35B is made for generating a highermagnetic field. Depending on the direction of the current in the sharedcolumn line 34, it is established which one of two binary values, e.g.“0” or “1”, will be written in a selected memory element 32. Thecombination in the selected magnetoresistive element 32B of the magneticfields generated by current in an appropriate shared column line 34, inan appropriate supplementary column line 36B and in an appropriate rowline 37, provides a magnetic field able to change the direction of themagnetic vector of the free layer of this selected memory element 32B.Either of the magnetic fields by itself, or a combination of not allthose magnetic fields, is not able to change the storage state.Therefore only the selected memory cell 31 is written even though theshared column line provides a magnetic field in the memory elements 32of two adjacent columns 35A, 35B. A power supply (not represented)provides the necessary power for generating the row currents, the columncurrents and the supplementary column currents. Only a limited number ofmemory cells 31 are shown in FIG. 4, but in practice the memory array 30can be of any size.

As illustrated in FIG. 11, to select the current direction in the columnline 34 and in the supplementary column lines 36A, 36B, a couple ofcurrent direction switches SL1, SL1 , SL2, SL2 , such as e.g.semiconductor switches or transistors, and a switching mechanism (notrepresented in FIG. 11) for switching the current direction switches areprovided. Depending on whether a value needs to be written in memoryelement 32A or in memory element 32B, and depending on the value to bewritten, the current direction switches are brought into an appropriatestate (open or closed) by the switching mechanism.

If a first binary value, for example a “0”, needs to be written e.g. inmemory element 32B, as an example it may for example be needed to have acurrent of −1 mA in supplementary column line 36A, a current of −1 mA inshared column line 34 and a current of 2 mA in supplementary column line36B. A power supply 41 provides the necessary power for generating thenecessary currents. Switches SL1 and SL2 in a state so as to be able toconduct current, e.g. they are closed, and switches SL1 and SL2 are in astate so as to block current, e.g. they are opened. The current 2.I,provided by the current source 40 is divided over the supplementarycolumn line 36A and the shared column line 34, and is recombined andreturned to supplementary column line 36B. It is to be noted that, inthe embodiment represented in FIG. 11, all current lines 34, 36A, 36Bare connected by a simple short-circuit at one side of the memorymatrix.

The full logic functions for the switches SL1, SL2, SL1 and SL2 , i.e.for writing the logic values in both elements 32A, 32B, are shown in thetables hereinunder. SL1 and SL1 are in an inverse state respectively,i.e. if one is conducting, the other is not, and SL2 and SL2 are in aninverse state respectively.

SL1 0 1 Element 32A 0 1 Element 32B 1 0 SL2 0 1 Element 32A 0 0 Element32B 1 1

The switches SL1, SL2, SL1 and SL2 do not simply determine the polarityof the current in the current lines 32A, 32B,34 when selected. Dependingon whether left or right elements 32A, 32B are to be written, thefunction of the switches SL1, SL1 is reversed. A possible alternativewould be to use a different magnetisation state for storing a logicvalue in left and right elements, i.e. for the left elements 32A a firstmemory state, e.g. “0”, would mean e.g. “magnetisation-to-the-left”,whereas for right elements 32B a first memory state, would mean“magnetisation-to-the-right”.

The switches SL2 and SL2 distinguish between writing on the right andleft elements 32A, 32B respectively, on a shared column line 34.

Different bit-specific current source/sink units can be combined into alarger entity for word-parallel writing. This is schematicallyrepresented in FIG. 12. The current driver is then simply responding tothe data to be written in the following way. In e.g. an 8-bit version,upon receipt of the word 10000110, the switches SL1, SL2, SL1 , SL2 areclosed for the sequence of bits in an appropriate way so as to be ableto write the sequence 1-0-0-0-0-1-1-0 in subsequent bits. Since left andright bits on a shared current line cannot be written simultaneously,the write operation can be performed in two steps, by first writing theodd bits of the word (left elements=1-0-0-1), followed by the even bits(right elements=0-0-1-0). All switches SL2, SL2 can then be controlledusing a single signal line for the whole matrix, e.g. odd/even.

According to an embodiment of the present invention, making use of theintrinsic resistance equality in the different channels, a singlecurrent source (with level ˜n.I) may be used, rather than n/2 differentsmaller current sources (level ˜2.I). The principle is sketched in FIG.13. The decision about the ultimate implementation should be based on asmaller variation in the current line resistance values, rather than thedifferent current source levels. In other words, when the statisticalvariation in the resistance of the different current loops is verysmall, a single current source built around an enlarged-gate transistormay give a better control over the current levels in the differentloops.

FIG. 14 shows a serial approach by feeding the current sink of the firstpair of bits into the current source of the second pair, etc. If each ofthe switches SL1, SL2, SL1 , SL2 are appropriately switched, the rightcontent can be simultaneously written to one bit of each pair of bits.Therefore, a smaller current source 40 proves to be adequate, thussaving substrate area, e.g. silicon area. In this approach, theadvantages of a smaller power consumption are combined with a fast writetime and a low peak current. In a modular approach for MRAM, smallermemory banks or blocks may be used to reduce the overall current lineresistance. This is typically done to reduce voltage losses over thecurrent lines.

An additional way of writing data can be introduced for word-parallelwriting. In this case, all the odd bits, i.e. the left bits 32A of eachshared column line are written first, followed by the even bits, i.e.the right bits 32B. All switches SL2, SL2 can then be controlled using asingle signal line for the whole matrix, e.g. odd/even.

Since, in this case, the writing of even and odd bits has to beseparated, two words can be interleaved. A memory bank then consists oftwice the number of bits in a word. Supposing that an 8-bit word isused, two different words can be written on one line, hence 16 bits intotal.

For example:

-   word 1, for the left bits: 0 1 1 0 1 1 0 0-   word 2, for the right bits: 1 1 1 1 0 0 0 0-   interleaved, this gives: 01 11 11 01 10 10 00 00    The switch sequence would then be, as a function of time:

writing of word 1 writing of word 2 SL1 -01101100- -00001111- SL1-10010011- -11110000- SL2 -0- -1- SL2 -1- -0-

FIG. 6 shows the magnetic field component profile, orthogonal to theselected current lines 34, 36A, 36B, for the embodiment of FIG. 5, withcurrent values as given in Table 1. By proper choice of current linedimensions, as in Table 1 above, the magnetic field extreme value can belocalized at one of the devices 32A, 32B, in the example given at device32B. Graph 50 is a graph in case a current through the shared columnline 34 is simply returned through the supplementary column line 36Bcorresponding to the selected column 35B. It is to be noticed that ahigh magnetic field is generated at the selected memory element 32B.Unfortunately, the magnetic field at a neighboring, non-selected bit ormemory element 32A is also rather high in this configuration. A goodestimate is that the field there is about half the size as for theselected bit or memory cell 32B, as can also be seen in graph 50 of FIG.6. The magnetic field at the non-selected memory element 32A can bedecreased by using the supplementary column line 36A corresponding tothe non-selected column 35A. Current is sent through the shared columnline 34 and the supplementary column line 36A corresponding to thenon-selected column 35A, thus effectively creating an opposite field atthe non-selected memory element 32A, so that the cross-talk issuppressed, and is returned to the supplementary column line 36Bcorresponding to the selected column 35B. This way, the magnetic fieldat the non-selected element 32A maybe reduced to ˜25% of the maximumfield, as represented in graph 51 of FIG. 6. The field profile may befurther improved by proper choice of the geometry, i.e. current, width,height, offset, overlap, etc. while taking into account geometricalconstraints imposed by advanced semiconductor design.

FIG. 7 shows a 3-dimensional magnetic field profile, i.e. magnitude infunction of position and direction, in case no current is sent throughthe supplementary column line 36A of a non-selected column 35A. In theexample given, the current in the column line 37 was chosen such thatboth magnetization components used for writing are equal, giving theoptimal noise margin. The potentially disturbing half-select fields 60,at 70% of maximum 2-dimensional field amplitude, i.e. comprising onlyone field component, are clearly visible.

Power consumption is analyzed. Supposing that the original current line4 (corresponding to the hatched part of column line 34 in FIG. 5) has aresistance R, it can be assumed that the resistance of the wider currentline 34 according to the present invention is approximately R/2.5.

If a current I is sent through a current line with resistance R, thecurrent line having the same width as a memory element and being placedsymmetrically with respect to that memory element, then the power neededto generate a magnetic field H in the memory element is R.I². If powerefficiency is defined as the ratio between the power consumption togenerate a magnetic field, and the generated magnetic field itself, thepower efficiency for this situation is (R.I²)/H. In order to obtain amagnetic field 2H with this-configuration, a current 2I can be sentthrough the current line. The power needed then is R.(2I)², and thepower efficiency is 2. R.I²/H. If, however, a current I is sent througha column line, and a corresponding return current is sent through areturn path, the memory element, the column line and the return pathhaving the same width and being placed symmetrically with respect toeach other, the power needed to generate a magnetic field 2H in thememory element is (R.I²+R.I²), and the power efficiency is(R.I²+R.I²)/(2H), or thus (R.I²)/H. This means that by using afunctional return path, i.e. a return path which substantiallycontributes to the generation of a magnetic field in a selected memorycell, magnetic fields generated in the magnetic memory cells are doubledfor a same power consumption.

Or thus, by sending current through the shared column line 34 and thesupplementary column line 36B corresponding to the selected column 35B(as graph 50 in FIG. 6), the field magnitude can be increased by 40% fora same current, while the power consumption is reduced by 20%(2(R/2.5)I² versus RI²). For a return path, which would be equallycontributing to the total field, a higher increase of magnetic field canbe obtained. However, for a same power consumption, the field isincreased by 50% by scaling of the current level.

When using a first supplementary column line 36B increasing the magneticfield in a selected column 355B and a second supplementary column line36A decreasing the magnetic field in an adjacent, non-selected column35A, the current levels can be chosen such that all the current is sentthrough column line 36B and then distributed over 34 and 36A, in aparallel way. For current levels taken from Table I, power consumptionis increased with a factor 3 with respect to the original digit linedesign, which results in an effective field gain of 1.9. To realize thisgain in the original design, linear current scaling would lead to afactor 3.6 increase in dissipation, which would exceed theelectromigration limit. Again, for a same dissipation, this would stillresult in a 21.5% effective field increase.

Power consumption Total power Ref. Max. Field for one field consumptionNo. Current (kA/m/mA) component only (incl. bit line) Simple line  4  1mA 0.782 - 100% R.I² 2.R.I² Line with return (not  1 mA 1.522 - 200%2.R.I² 3.R.I² shown) −1 mA Wider line with 34  1 mA 1.066 - 140%2.(R/2.5).I² = 1.8.R.I² Return (offset) 36B −1 mA 0.8.R.I² Same width 34 1 mA 1.627 - 210% (R/2.5).(I² + (2.I)²) = 3.R.I² diff. current 36B −2mA 2.R.I² levels Same width 34  1 mA 1.470 - 190% (R/2.5).(2.I² +(2.I)²) = 3.4.R.I² diff. Current 36A  1 mA 2.4.R.I² levels 36B −2 mA(cfr Table I)

The maximum achievable magnetic field using a shared digit line can beup to 10 kA/m as calculated by linearly scaling the obtained results,taking into account that the maximum current density should not exceed10⁷ A/cm² or, in other words, 1 mA per (100 nm)² line section. Themaximum current in column line 36B is therefore limited to 12 mA in theexample given.

According to a further embodiment of the present invention, flux guidingcladding layers 70, 71 (FIG. 8) may be provided at the column lines 34,at the supplementary column lines 36A, 36B and/or at the row lines 37.These flux guiding cladding layers 70, 71 are of a high permeability andmagnetically soft (low coercivity), such as e.g. nickel iron (NiFe).These flux guide cladding layers 70, 71 lead to a better localization ofthe magnetic field into the area of the selected cell. A gain of factor2 in field magnitude can be realized this way. Moreover, the selectivityto neighboring memory elements 32 is enhanced, and thus cross-talk inneighboring memory elements 32 is reduced by using such flux guidingcladding layers 70, 71. The flux guiding cladding layer 70, 71 may coveronly one side of a row line 37, column line 34, or supplementary columnline 36A, 36B, preferably the side away from the memory element 32, orit may cover up to three sides thereof (as shown in FIG. 8) for maximumefficiency. The use of magnetic cladding layers 70, 71 increasesmagnetic field levels. Moreover, the magnetic field homogeneityimproves, while cross-talk to the neighboring bit can be greatlyreduced. In this embodiment, this would mean that the current in thesupplementary column line 36A to reduce the field at the non-selectedbit or memory element 32A can possibly be chosen smaller, or evenomitted.

The implementation of magnetic cladding layers 70, 71 in current linesas described in this invention disclosure becomes technologicallysimpler in comparison to previous integration schemes. Due to thestrongly increased current line cross-section, the effective loss ofcross-section by implementing cladding layers 70, 71 is rather limited,which makes it a far more attractive option.

It is to be understood that although preferred embodiments, specificconstructions and configurations, as well as materials, have beendiscussed herein for devices according to the present invention, variouschanges or modifications in form and detail may be made withoutdeparting from the scope and spirit of this invention.

1. An array with magnetoresistive memory cells arranged in logicallyorganized rows and columns, each memory cell including amagnetoresistive element, the matrix comprising a set of column lines,the column lines provided with a flux guiding cladding layer, a columnline being a continuous conductive strip which is magnetically coupledto the magnetoresistive element of each of the memory cells of a column,a column line being shared by two adjacent columns, the shared columnline having an area which extends over substantially themagnetoresistive elements of the two adjacent columns sharing thatcolumn line, the shared column line having a height smaller than width,the array furthermore comprising at least one supplementary column lineper column for generating a localized magnetic field in themagnetoresisive elements of one of the adjacent columns sharing thecolumn line.
 2. The array of claim 1, wherein a supplementary columnline forms a return current path for current carried by a column line.3. The array of claim 1, wherein a column line and a supplementarycolumn line are provided at opposite sides of a column ofmagnetoresistive elements.
 4. The array of claim 1, wherein a column ofmagnetoresistive elements is placed offset in a row-direction withregard to a center of a supplementary column line.
 5. The arrayaccording to claim 1, wherein the supplementary column line is providedwith a flux guiding cladding layer.
 6. Non-volatile memory comprisingthe array with magnetoresistive memory cells of claim
 1. 7. An arraywith magnetoresistive memory cells arranged in logically organized rowsand columns, each memory cell including a magnetoresistive element, thematrix comprising a set of column lines, the column lines provided withflux guiding claddling layer, a column line being a continuousconductive strip which is magnetically coupled to the magnetoresistiveelement of each of the memory cells of a column, a column line beingshared by two adjacent columns, the shared column line having area whichextends over substantially the magnetoresistive elements of the twoadjacent columns sharing that column line, the shared column line havinga height smaller than width, the array furthermore comprising at leastone supplementary column line per column for generating a localizedmagnetic field in the magnetoresistive elements of one of the adjacentcolumns sharing the column line; and a set of row lines, the row linesprovided with a flux guiding cladding layer, each row line being acontinuous conductive strip which is magnetically coupled to themagnetoresistive element of each of the memory cells of a row.
 8. Amethod of writing an array with magnetoresistive memory cells arrangedin logically organized rows and columns, each cell including amagnetoresistive element, comprising: applying current to a row line,applying current to a column line having a flux guiding cladding layerand having a height smaller than width, and shared by two columns, andapplying current to at least one supplementary column line forgenerating a localized magnetic field in one of the memory elements onthe column line.
 9. A method of manufacturing an array withmagnetoresistive memory cells, comprising: providing magnetoresistivememory cells arranged in logically organized rows and columns, each cellincluding a magnetoresistive element, providing a set of column lines,the column lines having a flux guiding cladding layer, a column linebeing a continuous conductive strip which is magnetically coupled to themagnetoresistive element of each of the memory cells of a column, acolumn line being shared by two adjacent columns, the shared column linehaving an area which extends over substantially the magnetoresistiveelements of the two adjacent columns sharing that column line, theshared column line having a height smaller than width, providing atleast one supplementary column line per column for generating alocalized magnetic field in the magnetoresistive elements of one of theadjacent columns sharing the column line.